Chiplet technology is a key approach for extending Moore's Law.
However, its design process is constrained by two primary challenges:
- the scarcity of early-stage platforms for rapidly evaluating chiplet-based heterogeneous systems,
- and the complex relationships between design parameters and optimization metrics.
To address these challenges, we propose a synergistic framework that integrates a Large Language Model (LLM) with Bayesian Optimization (BO), enabling architectural-level simulation and automated optimization for the 2.5D/3D CPU-GPU heterogeneous chiplets.
We extend the open-source chiplet simulator to evaluate 3D designs by supporting graph topologies.
Further, to enhance the exploration efficiency of BO, we introduce an LLM that generates high-quality policies to guide the optimization process, enabled by our proposed adaptive directional policy reasoning (ADPR) and an exploration gain-aware fine-tuning method.
Finally, we use the policy-guided BO to perform an automated and efficient exploration of the complex chiplet design space.
Experiments on 2.5D and 3D chiplet reveal that our framework improves design space exploration efficiency.